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2.1 The Design Flow: Specification, Logic Design, Physical Design, and Verification

Chapter Introduction Video 

Lecture Video 2.1

I. The Architecture of Semiconductor Design

II. Upstream Enablers: Electronic Design Automation (EDA)

III. Reusable Blocks: Core IP and the "LEGO" Analogy

IV. Bridging Design and Fabrication: The PDK

V. The Design Milestone: Tape-Out

VI. Where Design Value Is Created

2.2 Upstream Enablers: Oligopolistic Dominance in EDA and Licensable ISAs

Lecture Video 2.2

I. The EDA Triopoly: Software as a Chokepoint

II. The Architecture of Dependency: Switching Costs

III. Licensable Architectures: The Power of the ISA

IV. The Open-Source Challenger: RISC-V

V. The Design-to-Cost Trade-Off

2.3 Wafer Fabrication (Front-End): The Iterative Cycle of FEOL and BEOL

Lecture Video 2.3

I. The Fabrication Environment: Cleanrooms and Automation

II. Front-End-of-Line (FEOL): Transistor Construction

III. The Iterative Cycle: Layering Through Photolithography

IV. Back-End-of-Line (BEOL): Metal Interconnects

V. Lead-Time Arithmetic: The DPML Metric

VI. The Practical Challenge: Reentrancy and Bottlenecks

2.4 Assembly, Test, and Packaging (Back-End): Converting Wafers Into Finished Chips

Lecture Video 2.4

I. The Transformation Flow: From Wafer to Device

II. The OSAT Business Model: Outsourcing the Back-End

III. Advanced Packaging: Blurring the Lines

IV. Practical Strategy: Postponement and the Die Bank

2.5 Segment Economics: Margin Profiles and the "Smiling Curve" Critique

Lecture Video 2.5

I. The Architecture of Value: Defining "Value Added"

II. The "Smiling Curve" and Its Limitations

III. The Production Intensity Critique

IV. The Reinvestment Cycle: Tangible vs. Intangible

V. The Barrier of Scale

2.6 Lead-Time Arithmetic: Calculating the Gap From Design to Delivery

Lecture Video 2.6

I. The Design Milestone: From Concept to Tape-Out

II. Front-End Arithmetic: DPML and Node Complexity

III. The Waiting Game: Understanding the X-Factor

IV. Cumulative Lead Time and Purchase Obligations

2.7 Visibility and Dependencies: Identifying Single-Source Chokepoints

Lecture Video 2.7

I. The Anatomy of a Chokepoint

II. Equipment Monopolies: The ASML Factor

III. The Chemistry Chokepoint: Japanese Dominance

IV. Requalification Arithmetic: The PCN Hurdle

V. Geographic Concentration as a Chokepoint

Knowledge Check

Knowledge Check: Semiconductor Design Architecture

Knowledge Check2: EDA Tools and Design Enablement

Knowledge Check3: Core IP, PDKs, and Tape-Out

Knowledge Check 4: EDA Market Concentration

Knowledge Check 5: Switching Costs and ISA Licensing

Knowledge Check 6: RISC-V and Design-to-Cost Decisions

Knowledge Check 7: Cleanrooms, FEOL, and Transistor Construction

Knowledge Check 8: Photolithography and BEOL Interconnects

Knowledge Check 9: DPML, Reentrancy, and Fab Bottlenecks

Knowledge Check 10: Wafer-to-Device Transformation

Knowledge Check 11: OSAT and Advanced Packaging

Knowledge Check 12: Postponement and Die-Bank Strategy

Knowledge Check 13: Value Added and the Smiling Curve

Knowledge Check 14: Production Intensity and Reinvestment

Knowledge Check 15: Design-to-Delivery Lead-Time Arithmetic

Knowledge Check 16: Chokepoint Identification

Knowledge Check 17: Equipment and Chemistry Dependencies

Knowledge Check 18: PCN Requalification and Geographic Risk

Welcome to the "Semiconductor Value Chain from Design to Delivery" course, your comprehensive guide to understanding the intricate journey of microchips from initial concept to final product. In today's technology-driven world, semiconductors are the bedrock of modern electronics, powering everything from smartphones to advanced AI systems.

Welcome to the "Semiconductor Value Chain from Design to Delivery" course, your comprehensive guide to understanding the intricate journey of microchips from initial concept to final product. In today's technology-driven world, semiconductors are the bedrock of modern electronics, powering everything from smartphones to advanced AI systems. However, the supply chain behind these critical components is notoriously complex, highly specialized, and fraught with geopolitical and economic dependencies. This course demystifies the entire semiconductor lifecycle. You will explore the foundational design flow, including logic and physical design, and understand the critical role of Electronic Design Automation (EDA) and licensable Instruction Set Architectures (ISAs) like RISC-V. We will dive deep into the front-end wafer fabrication process, examining the iterative cycles of FEOL and BEOL, and the immense challenges of cleanroom environments and photolithography. Moving to the back-end, you will learn about assembly, testing, packaging, and the evolving OSAT business model. Furthermore, this course provides a rigorous analysis of segment economics, challenging the traditional "Smiling Curve" and exploring margin profiles, production intensity, and barriers of scale. Finally, you will master lead-time arithmetic to accurately calculate the gap from design to delivery, and identify critical single-source chokepoints, such as equipment monopolies and geographic concentrations, that threaten global supply chains. Whether you are a supply chain professional, a tech investor, or an industry enthusiast, this course equips you with the strategic insights needed to navigate the semiconductor ecosystem.

Chapter 2: Semiconductor Value Chain from Design to Delivery

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            <p>The semiconductor industry is the bedrock of modern technology, operating through a highly complex and globally distributed value chain. This course provides an in-depth exploration of the entire lifecycle of semiconductor manufacturing, tracing the journey of a chip from its initial conceptual design to its final physical delivery. By examining the intricate architecture of semiconductor design, learners will uncover the critical roles played by upstream enablers such as Electronic Design Automation (EDA) tools, licensable Instruction Set Architectures (ISAs), and reusable Core IP. The curriculum demystifies the transition from digital blueprints to physical silicon, highlighting pivotal milestones like tape-out and the essential bridge provided by Process Design Kits (PDKs) that connect chip architects with fabrication facilities.</p>

<p>Beyond the design phase, the course delves into the rigorous physical realities of wafer fabrication, detailing the iterative cycles of Front-End-of-Line (FEOL) and Back-End-of-Line (BEOL) processes within highly automated cleanrooms. It further explores the back-end transformation where wafers are converted into finished chips through assembly, testing, and advanced packaging by Outsourced Semiconductor Assembly and Test (OSAT) providers. Crucially, the syllabus contextualizes these technical processes within the broader economic and strategic landscape. Participants will analyze segment economics, including the limitations of the "Smiling Curve," calculate complex lead-time arithmetic to understand the true gap from design to delivery, and identify critical single-source chokepoints—ranging from equipment monopolies like ASML to chemical dependencies and geographic concentrations—that define the vulnerabilities of the global semiconductor supply chain.</p>
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