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5.1 Marketing vs. Physics: How Node Designations Moved From Gate-Length Measurements to Generational Brand Labels

 Chapter Introduction Video 

Lecture Video 5.1

I. The Era of Physical Precision

II. The Decoupling of Names and Reality

III. PPA: The Manager's True Metric

IV. The Economic Break: Moore's Law at 28nm

V. Evaluating Roadmap Credibility

5.2 The 2nm-Class Architecture Shift: Gate-All-Around Nanosheets and RibbonFETs as the Answer to FinFET Leakage Limits

Lecture Video 5.2

I. The Exhaustion of the Fin

II. The GAA Revolution: Total Control

III. Competitive Architectures: Nanosheets and RibbonFETs

IV. Design Flexibility: The Power of Variable Widths

V. Practical Implication: First-Mover vs. Fast-Follower

5.3 Power Delivery Innovation: Backside Power Delivery (PowerVia, Super Power Rail) as a Solution to RC Delay in Overcrowded Metal Layers

Lecture Video 5.3

I. The "Plumbing" Crisis: RC Delay and Crowding

II. Backside Power Delivery: The Structural Solution

III. Competitive Implementation: PowerVia and Super Power Rail

IV. Practical Benefits: Density and Signal Integrity

V. Practical Implication: Selecting the Strategic Node

5.4 The Lithography Chokepoint: ASML's EUV Monopoly and the Move From 0.33 NA to 0.55 NA High-NA Systems

Lecture Video 5.4

I. The Physics of the Constraint: The Rayleigh Criterion

II. ASML: The Monopoly Architect

III. The High-NA Revolution: From 0.33 to 0.55

IV. Practical Economics: The US$400 Million Decision

V. The Backlog as a Macro Indicator

5.5 The Multi-Patterning Cost Wall: How the EUV Delay Forced Costly DUV Immersion Multi-Patterning and Broke Cost-per-Transistor Scaling

Lecture Video 5.5

I. The Broken Promise of Moore's Law

II. The DUV Immersion Gap

III. The Multi-Patterning Penalty

IV. The SRAM Scaling Penalty

V. The EUV and High-NA Economic Reset

5.6 Mature-Node Significance: Why 28nm and Above Account for 88% of Unit Volume and Support Critical Infrastructure in Defense and Automotive

Lecture Video 5.6

I. Defining "Legacy": The 28nm Threshold

II. The Volume-Versus-Value Paradox

III. Strategic Infrastructure and Critical Applications

IV. The Geopolitical Race for Capacity

V. Practical Implication: Price Wars and Sourcing Risk

5.7 Geopolitical Pressure on Legacy Nodes: How the Section 301 Investigation and the 2027 Tariff Deadline Affect Chinese Mature-Node Capacity

Lecture Video 5.7

I. The Section 301 Investigation: Unfair Trade and National Security

II. The 2027 Tariff Cliff: Navigating the Grace Period

III. Subsidized National Champions: Displacing Market Competition

IV. Dependency and Economic Coercion

V. Strategic Transformation: "Mature Isn't Safe"

5.8 Compound Semiconductors: The Rise of SiC and GaN for 800V EV Power Electronics and the Move to 200mm and 300mm Wafers

Lecture Video 5.8

I. Beyond Silicon: The Physics of Wide-Bandgap

II. Silicon Carbide (SiC) and the 800V EV Catalyst

III. Gallium Nitride (GaN): From Fast Chargers to Data Centers

IV. The Economics of Scaling: The Move to 200mm and 300mm Wafers

V. Sourcing Risk and Geopolitical Interventions

5.9 Evaluating Roadmap Credibility: Using Yield Disclosures, Customer Tape-Outs, and PDK Maturity to Vet Supplier Claims at the Leading Edge

Lecture Video 5.9

I. The PDK: The Foundry's First Commitment

II. The Tape-Out: The Point of No Return

III. Yield: The Silent Metric

IV. Ecosystem Enablement and Foundation IP

V. Sourcing Risk: The "Significant Customer" Requirement

5.10 Timing and Strategy: First-Mover Advantages in AI/HPC vs. the Fast-Follower Strategy of Extending Long-Lived Nodes Such as 7nm and 28nm

Lecture Video 5.10

I. The First-Mover Mandate: AI and HPC

II. The Fast-Follower Strategy: Yield and Maturity

III. The "Node of Choice" for a Decade: 28nm and 7nm

IV. Economic Bifurcation and Disaggregation

V. Practical Implication: Evaluating the "Significant Customer"

Knowledge Check

Question 1: Why are modern node designations best interpreted as generational labels rather than direct gate-length measurements?

Question 2: Which three factors are represented by the PPA framework used to compare process technologies?

Question 3: What electrostatic limitation of FinFETs motivates the transition to gate-all-around transistor architectures?

Question 4: How does a gate-all-around structure improve channel control compared with a FinFET?

Question 5: What design advantage do variable-width nanosheets provide for transistor performance tuning?

Question 6: What causes RC delay to become a critical constraint in advanced interconnect stacks?

Question 7: How does backside power delivery reduce congestion in frontside metal layers?

Question 8: According to the Rayleigh criterion, how does increasing numerical aperture affect lithographic resolution?

Question 9: What strategic trade-off should a manufacturer evaluate before purchasing a High-NA EUV system?

Question 10: Why does DUV immersion multi-patterning increase manufacturing cost and process risk?

Question 11: Why can SRAM scaling limit the density and cost benefits of a new logic node?

Question 12: Why do mature nodes remain strategically important despite lower transistor density?

Question 13: How can tariffs and subsidized capacity change sourcing risk for mature-node semiconductor buyers?

Question 14: Why are SiC devices especially valuable in 800V electric-vehicle power systems?

Question 15: Which evidence should a customer examine to evaluate the credibility of a leading-edge foundry roadmap?

Welcome to "Semiconductor Process Technology and Node Strategy," a comprehensive course designed to demystify the complex world of modern semiconductor manufacturing, node progression, and supply chain dynamics. In today's rapidly evolving tech landscape, understanding the shift from physical gate-length measurements to generational brand labels is crucial for industry professionals.

Welcome to "Semiconductor Process Technology and Node Strategy," a comprehensive course designed to demystify the complex world of modern semiconductor manufacturing, node progression, and supply chain dynamics. In today's rapidly evolving tech landscape, understanding the shift from physical gate-length measurements to generational brand labels is crucial for industry professionals. This course dives deep into the physics, economics, and geopolitics driving the semiconductor industry. You will explore the transition from FinFET to Gate-All-Around (GAA) Nanosheets and RibbonFETs, and understand how Backside Power Delivery (PowerVia) solves critical RC delay issues. We will also unpack the lithography chokepoint dominated by ASML's EUV and High-NA systems, and the economic realities of the multi-patterning cost wall. Beyond the leading edge, this course highlights the immense strategic value of mature and legacy nodes (28nm and above) which power 88% of unit volumes in automotive and defense sectors, alongside the geopolitical pressures shaping global capacity. Finally, you'll gain actionable insights into compound semiconductors like SiC and GaN for EV power electronics, and learn how to evaluate foundry roadmap credibility using PDK maturity, tape-outs, and yield disclosures. Whether you are navigating first-mover advantages in AI/HPC or fast-follower strategies, this course equips you with the strategic knowledge to make informed decisions in the semiconductor node race.

Chapter 5: Semiconductor Process Technology and Node Strategy

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            <p>The semiconductor industry is undergoing a profound transformation where traditional scaling metrics no longer apply. The transition from physical gate-length measurements to generational brand labels has fundamentally altered how process technology is evaluated and marketed. As Moore's Law faces unprecedented economic and physical barriers, the industry is pivoting toward groundbreaking architectural shifts to sustain performance improvements. Innovations such as Gate-All-Around (GAA) nanosheets, RibbonFETs, and backside power delivery networks are emerging as critical solutions to FinFET leakage limits and RC delay in overcrowded metal layers. Furthermore, the reliance on advanced lithography—particularly the transition to ASML's 0.55 NA High-NA EUV systems—underscores the immense capital and technical precision required to push the boundaries of the leading edge and overcome the multi-patterning cost wall.</p>

<p>Beyond the pursuit of the smallest nanometer, a comprehensive node strategy requires navigating complex economic and geopolitical landscapes. Mature nodes at 28nm and above continue to account for the vast majority of global unit volume, serving as the backbone for critical infrastructure in the defense and automotive sectors. However, these legacy nodes are increasingly subject to geopolitical pressures, including Section 301 investigations and looming tariff deadlines that threaten to reshape global capacity. Simultaneously, the rise of compound semiconductors like Silicon Carbide (SiC) and Gallium Nitride (GaN) is revolutionizing power electronics for 800V electric vehicles and high-demand data centers. To succeed in this multifaceted environment, industry leaders must rigorously evaluate foundry roadmap credibility through yield disclosures, Process Design Kit (PDK) maturity, and customer tape-outs, carefully balancing the high-stakes first-mover advantages in AI and HPC against the proven reliability of a fast-follower strategy on long-lived nodes.</p>
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