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3.1 The Four Pillars and Foundry 2.0: Comparing IDMs, Fabless, Pure-Play Foundries, and OSATs

Chapter Introduction Video

Lecture Video 3.1

I. An Analogy: The Book Business

II. The Integrated Device Manufacturer (IDM)

III. The Fabless Model: Design Without Fabs

IV. Pure-Play Foundries: The Manufacturing Engines

V. Outsourced Semiconductor Assembly and Test (OSAT)

VI. Worked Example: Same Revenue, Four Different Businesses

VII. Foundry 2.0 and the Integration Shift

3.2 Drivers of Disaggregation: Minimum Efficient Scale, Escalating Fab Costs, and the "Big Bang" Impact of EDA Tools

Lecture Video 3.2

I. Three Pressures That Split the Industry

II. The Escalating Cost of Fabrication

III. Minimum Efficient Scale and Demand Aggregation

IV. The "Big Bang" of EDA Tools

V. R&D Intensity Versus Capital Intensity

VI. Worked Example: How Many Wafers Does a Leading-Edge Fab Need?

3.3 Financial Fingerprints: 2025/2026 Performance Metrics Showing Leadership Rotation and Historical Segment Economics

Lecture Video 3.3

I. The Historical Baseline (2016–2019)

II. The 2025 Performance Peak

III. The Q1 2026 Leadership Rotation

IV. Profitability and the "Scarcity Gate"

V. Worked Example: How a Scarce Input Shifts Profit

3.4 Dependency and the Credibility Challenge: Managing Foundry Neutrality, IP Protection, and the Trust Barriers Facing IDM-Foundry Hybrids

Lecture Video 3.4

I. The Principle of Foundry Neutrality

II. Protecting Intellectual Property

III. The Credibility Challenge for IDM-Foundry Hybrids

IV. Capacity Allocation and the Conflict of Interest

Lecture Video 3.5

V. System-Level Integration and Deeper Lock-In

3.5 Chiplets and the UCIe Standard: How UCIe 3.0 Enables Multi-Vendor Integration and Shifts Value From Front-End Wafer Fabrication to System-Level Packaging

I. The End of the Monolithic Era

II. Worked Example: The Yield Case for Chiplets

III. UCIe: A Common Language for Chiplets

IV. The Value Shift to Advanced Packaging

V. Heterogeneous Integration and AI Performance

VI. Strategic Challenges: Security, Testing, and Thermals

3.6 Customer-Designed Silicon: The 2026 Shift Toward Hyperscaler ASICs, Sovereign AI Programs, and the Broadcom–Marvell Co-Design Duopoly

Lecture Video 3.6

I. The Economics of Make Versus Buy

II. Worked Example: How Many Chips Justify a Custom Design?

III. The Co-Design Model and the Broadcom–Marvell Duopoly

IV. The Hyperscaler Field Map

V. Beyond the Hyperscalers: AI Labs, Enterprises, and Sovereign Programs

VI. Practical Implication: The Dual-Track Strategy

3.7 The Make-vs-Buy Calculus: Analyzing the TCO Advantage, NRE Costs, and Multi-Year Design Risks

Lecture Video 3.7

I. Where the TCO Advantage Comes From

II. The Scale Barrier: NRE and Minimum Efficient Scale

III. The Timing Mismatch

IV. Worked Example: A Make-Versus-Buy Model With Risk Scenarios

V. Strategic Value Beyond Cost

VI. A Decision Framework

3.8 Strategic Lenses for Model Selection: Transaction Cost Economics, Core Competence, and the Strategic Value of Supply Sovereignty

Lecture Video 3.8

I. Lens 1: Transaction Cost Economics

II. Lens 2: Core Competence

III. Lens 3: Supply Sovereignty

IV. The Hybrid Middle Ground

V. Worked Example: Applying the Three Lenses

Knowledge Check

Knowledge Check 1: Identify the defining characteristics of the IDM business model.

Knowledge Check 2: Distinguish the fabless model from the pure-play foundry model.

Knowledge Check 3: Explain the role of an OSAT in the semiconductor value chain.

Knowledge Check 4: Compare how four semiconductor business models can generate similar revenue with different cost structures.

Knowledge Check 5: Analyze how escalating fabrication costs contributed to industry disaggregation.

Knowledge Check 6: Apply the concept of minimum efficient scale to foundry demand aggregation.

Knowledge Check 7: Explain how EDA tools changed the economics of semiconductor design.

Knowledge Check 8: Interpret the relationship between scarcity and segment profitability.

Knowledge Check 9: Evaluate why foundry neutrality is important to external customers.

Knowledge Check 10: Identify the intellectual-property and capacity-allocation concerns facing IDM-foundry hybrids.

Knowledge Check 11: Analyze the yield rationale for using chiplets instead of a monolithic die.

Knowledge Check 12: Explain how UCIe enables multi-vendor chiplet integration.

Knowledge Check 13: Evaluate the business implications of the value shift toward advanced packaging.

Knowledge Check 14: Calculate the volume threshold at which a custom ASIC may be economically justified.

Knowledge Check 15: Analyze TCO, NRE, and timing risks in a make-versus-buy decision.

Knowledge Check 16: Apply transaction cost economics, core competence, and supply sovereignty to select a semiconductor business model.

Welcome to "Semiconductor Business Models and Strategic Integration," a comprehensive online course designed to decode the complex and rapidly evolving semiconductor supply chain. The global semiconductor industry is undergoing a massive structural transformation.

Welcome to "Semiconductor Business Models and Strategic Integration," a comprehensive online course designed to decode the complex and rapidly evolving semiconductor supply chain. The global semiconductor industry is undergoing a massive structural transformation. From the emergence of Foundry 2.0 and advanced chiplet architectures to the rise of hyperscaler ASICs and sovereign AI programs, understanding these strategic shifts is critical for anyone involved in technology, manufacturing, or investment. This course dives deep into the four foundational pillars of the industry: Integrated Device Manufacturers (IDMs), Fabless firms, Pure-Play Foundries, and Outsourced Semiconductor Assembly and Test (OSAT) providers. We will explore the historical and economic drivers of industry disaggregation, including escalating fabrication costs, minimum efficient scale, and the "Big Bang" impact of EDA tools. You will analyze real-world financial fingerprints, leadership rotations, and the unique credibility challenges facing IDM-Foundry hybrids regarding IP protection and foundry neutrality. Furthermore, the course unpacks the revolutionary shift toward advanced packaging enabled by the UCIe 3.0 standard and the complex make-versus-buy calculus for custom silicon design. By applying strategic frameworks such as transaction cost economics, core competence, and supply sovereignty, you will gain the analytical tools needed to navigate and lead in the modern semiconductor landscape. Enroll today to master the economics, strategies, and future trends shaping the silicon that powers our world.

Chapter 3: Semiconductor Business Models and Strategic Integration

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            <p>The semiconductor industry has undergone a profound structural transformation, evolving from a landscape dominated by vertically integrated monopolies to a highly specialized, disaggregated global ecosystem. This course, "Semiconductor Business Models and Strategic Integration," explores the fundamental architecture of this ecosystem by examining the four foundational pillars: Integrated Device Manufacturers (IDMs), Fabless firms, Pure-Play Foundries, and Outsourced Semiconductor Assembly and Test (OSAT) providers. By analyzing the historical drivers of this disaggregation—such as escalating fabrication costs, the necessity of minimum efficient scale, and the revolutionary impact of Electronic Design Automation (EDA) tools—learners will uncover how and why the industry fragmented, and how these distinct business models interact to drive modern technological advancement.</p>

<p>Beyond the traditional frameworks, the curriculum delves into the next frontier of semiconductor strategy, often referred to as Foundry 2.0. As traditional scaling faces physical and economic headwinds, value is rapidly shifting from front-end wafer fabrication to system-level advanced packaging. We will investigate the rise of chiplet architectures, the unifying UCIe standard, and the surge in customer-designed silicon driven by hyperscalers and sovereign AI programs. Through practical frameworks like the Make-vs-Buy calculus, transaction cost economics, and core competence analysis, participants will gain the analytical tools necessary to navigate complex strategic decisions, manage intellectual property risks, and evaluate the financial fingerprints that dictate market leadership in the 2025/2026 landscape and beyond.</p>
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